In typical multi-layer semiconductor device, electrical interconnects including vias, interconnect lines, and bonding pads are formed in dielectric layers by embedding a conductive material in openings formed in the dielectric layer.
A process wafer typically includes a semiconductor substrate including active semiconductor devices formed thereover, followed by the formation of multiple layers of conductive wiring including vias and trench lines, and including uppermost layers having bonding pads for subsequent electrical interconnection by various methods to external circuits.
Following device formation in individual die areas on a wafer, the process wafer is subjected to various operations including wafer acceptance testing (WAT), dicing operations to form individual die, die interconnection bonding processes into packaged chips and the like, where the multi-layer device is subjected to both thermal and mechanical stresses including shear force components directed parallel to a layer thickness. The shear forces applied to the semiconductor device by the various processing operations can lead to catastrophic peeling of one or more layers of the multi-layer semiconductor device.
The problem is exacerbated where low-K (low dielectric constant) dielectric layers are used, as the low-K materials are typically less mechanically robust and have poor adhesion to overlying material layers. For example, the shear modulus (resistance to shear force) of the multi-layer device is crucial during die formation and assembly into packaged chips. While prior art approaches have been proposed to solve this problem, the approaches to date have been less than adequate in forming a multi-layer semiconductor device with adequate resistance to shear forces, leading to less than adequate device yield and reliability.
There is therefore a need in the semiconductor device integrated circuit manufacturing art to develop a multi-layer semiconductor device including embedded conductive features with improved structural stability and resistance to shear forces.
It is therefore an object of the invention to provide a multi-layer semiconductor device including embedded conductive features with improved structural stability and resistance to shear forces, while overcoming other deficiencies and shortcomings of the prior art.